Entry point for the program.
Calls to handle CLI options, parsing, generating and writing.
Source code in titan/main.py
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76 | def main():
""" Entry point for the program.
Calls to handle CLI options, parsing, generating and writing.
"""
args = run_argparse()
compiler_ctx = CompilerContext(args)
logging.basicConfig(
level=logging.DEBUG if compiler_ctx.user_wants_verbose_info else logging.INFO,
handlers=[
logging.FileHandler("compiler_log.txt"),
# logging.StreamHandler()
RichHandler(show_time=False, markup=True)
],
# format=f"[%(levelname)s] [%(module)s.%(funcName)s, line: %(lineno)d]: %(message)s"
format=f"%(message)s"
)
logging.info(f"--- New run, time is: {datetime.datetime.now().strftime('%d/%m/%Y %H:%M:%S')} ---")
logging.debug(f"arguments: {args}")
logging.debug(f"output folder exists? {os.path.exists('output')}")
os.makedirs("output", exist_ok=True)
logging.info(f"Generating SPIR-V from {compiler_ctx.files[0]}")
spirv_assembler = SPIRVAssembler(compiler_ctx.files[0], disable_debug=False)
spirv_assembler.compile()
if compiler_ctx.user_wants_spirv_asm:
spirv_assembler.output_to_file(os.path.basename(compiler_ctx.files[0])[:-3])
# early exit, no need for RTL
if compiler_ctx.user_only_wants_spirv:
return
logging.info(f"Generating HDL")
verilog_assembler = VerilogAssember(spirv_assembler.create_file_as_string())
verilog_assembler.compile(os.path.basename(compiler_ctx.files[0])[:-3],
gen_yosys_script=compiler_ctx.gen_yosys_script,
dark_dots=compiler_ctx.use_dark_theme_for_dots,
create_comms=compiler_ctx.gen_comms
)
|